1. Field of the Invention
The invention relates to a process for producing a flat semiconductor wafer for the semiconductor industry, in particular for fabricating electronic components with line widths of less than or equal to 0.13 μm.
2. Background Art
Semiconductor wafers which are suitable for the fabrication of electronic components with line widths of less than or equal to 0.13 μm must meet a large number of demanding property parameters. One especially important parameter is the geometry of the semiconductor wafer, which is to be understood as meaning, in particular, the flatness and the plane-parallelism of the faces of the semiconductor wafer. Some of the specification parameters describing the flatness can be categorized on the basis of the lateral extent of potential interference effect relating to it. In this context, a general distinction is drawn between global flatness (lateral extent in the region of the diameter of the semiconductor wafer/vertical deviation from an ideally flat surface), local flatness (lateral extent in the cm range/vertical effect in the 100 nm range), nanotopography (lateral mm range/vertical 10 nm range) and surface roughness (lateral μm range/vertical sub-nm range).
The definitive flatness of a semiconductor wafer is generally produced by a polishing process. Apparatuses and processes for the simultaneous polishing of front and back surfaces of semiconductor wafers have been provided and further developed with a view to improving the flatness parameters of a semiconductor wafer. Such double-side polishing is described, for example, in U.S. Pat. No. 3,691,694. In accordance with an embodiment of double-side polishing in EP 208 315 B1, semiconductor wafers in carriers made from metal or plastic having suitably dimensioned cutouts are moved between two rotating polishing plates, which are covered with a polishing cloth, along a path predetermined by the machine and process parameters, in the presence of a polishing fluid, and are thereby polished. In the relevant literature, carriers are also referred to as templates. To enable the compressive forces which are employed during double-side polishing to act preferentially on the semiconductor wafer that is to be polished and not on the carrier, the final thickness of semiconductor wafers which have been double-side polished in accordance with prior art is significantly greater than the thickness of the carriers used. U.S. Pat. No. 6,458,688 describes a process in which the thickness of the carriers, the thickness of the semiconductor wafers and the removal of material brought about by the polishing are maintained in a specific relationship in order to obtain particularly flat semiconductor wafers whose local geometry values are below a required threshold value and which do not differ significantly in an edge region of the semiconductor wafer from those in a center region.